Dynamic logic circuits in which the output state is determined during an evaluate phase of a clock signal are susceptible to charge sharing noise. In such logic circuits, the output logic state of the circuit is controlled by stacks of MOS devices which drain charge from a common node during the evaluation phase of operation of the circuit. The state of each stack of devices is determined by the inputs to the MOS devices comprising the stack. The noise results from the sharing of charge on the common node among the stacks of MOS devices. If the charge drained from the common node is sufficiently large, the output logic state may switch even though the input logic states are such that the output logic state would not otherwise switch in the absence of these parasitic effects. This may be better understood by now referring to FIG. 1 which typifies such a dynamic logic circuit.
Clock input 111 is applied to the gate of P-type MOS device 101. The source of MOS device 101 is coupled to a supply voltage, Vcc, and the drain of MOS device 101 is coupled to the input 117 of inverter 107. The output of inverter 107 forms the output 171 of the dynamic logic circuit 100. P-type MOS device 108 comprises a weak latch which latches the logic state of the input 117 of inverter 107. The junction between the drain of MOS device 101 and MOS device stacks 131 and 132 forms pre-charge node 121. The input 117 of inverter 107 is also connected to pre-charge node 121. MOS device stacks 131 and 132 are in parallel between pre-charge node 121 and ground.
The state of pre-charge node 121 depends on the logic states of the inputs to MOS devices 102, 103, 122, and 123. When the logic level of clock 111 is low, defining the pre-charge phase, MOS device 101 conducts, charging pre-charge node 121, and therefore the input 117 of inverter 107, to a high logic state. At the same time, the low logic level of clock 111 turns off clock foot MOS devices 104 and 105. This lifts MOS device stack 131 and MOS device stack 132 from ground. Therefore, pre-charge node 121 is charged to approximately Vcc during the low logic level of clock 111 independent of the input states of MOS devices 102, 103, 122, and 123.
The evaluate phase begins when clock 111 transitions from low to high. This turns off MOS device 101 and turns on clock foot MOS devices 104 and 105. This couples to ground the series strings of MOS devices 102 and 103 in MOS device stack 131, and MOS devices 122 and 123 in MOS device stack 132.
The state of pre-charge node 121 is determined by the logic signals applied to MOS devices 102, 103, 122, and 123 at their respective inputs 112, 113, 127, and 128. For example, in dynamic logic circuit 100, if input 112 and input 113 are both logic level high, MOS device 102 and MOS device 103 both conduct, discharging pre-charge node 121 to ground thereby forming a logic level low at the input 117 of inverter 107. The output 171 of dynamic logic circuit 100 would then be high. Likewise, if the logic levels of input 127 and input 128 are both high, then MOS device stack 132 would shunt pre-charge node 121 to ground, resulting in a logic high at the output 171 of dynamic logic circuit 100. Conversely, if either of the inputs 112 and 113 in MOS device stack 131, and inputs 127 or 128 in MOS device stack 132 are low, then neither MOS device stack 131 nor MOS device stack 132 has a conducting path to ground and pre-charge node 121 remains charged to a high logic level. Consequently, the output 171 of dynamic logic circuit 100 would remain at a low logic level.
It is an important requirement of the dynamic logic circuit 100 that the evaluate phase persists throughout the high state of clock 111. This means that the logic levels of inputs 112, 113, 127, and 128 may, and must be allowed to, attain their dynamic logic levels at any time during the high logic level state of clock 111 comprising a particular evaluate phase. The changing of the states of inputs 112, 113, 127, and 128 during the evaluate phase, coupled with real circuit effects, can give rise to noise in the operation of dynamic logic circuit 100.
If, in the evaluate phase, input 113 of MOS device 103 and input 128 of MOS device 123 are low and remain low, pre-charge node 121 should remain charged to a high logic level independent of the states of inputs 112 and 127. This is in accordance with the operation described above. However, if, during the evaluate phase, input 112 of MOS device 102 transitions from low to high, and input 127 of MOS device 122 also transitions from low to high, then both MOS device 102 and MOS device 122 turn on. Node 141 and node 142 are then both connected to pre-charge node 121. Due to stray capacitances, the charge on pre-charge node 121 divides between node 141 and node 142. This may reduce the charge on pre-charge node 121 to a level that is sufficiently low to cause the output 171 of dynamic logic circuit 100 to falsely switch. In order to overcome this effect, the dynamic logic circuit 200 of FIG. 2 has been employed.
Referring now to FIG. 2, it will be seen that dynamic logic circuit 200 employs circuitry to pre-charge any stray capacitances of node 141 and node 142. During the pre-charge phase, at which time pre-charge node 121 is charged through MOS device 101 by virtue of clock 111 being at a low logic level, clock 111 is also provided to the gates of MOS device 201 and MOS device 202. Thus, MOS devices 201 and 202 are turned on, thereby charging node 141 and node 142, respectively, to approximately Vcc. After the evaluate phase commences on the transition of clock 111 to a high logic level, ideally, node 141 and node 142 retain their pre-charge. In this circumstance, even if input 112 of MOS device 102 and input 127 of MOS device 122 transition from low to high during the evaluate phase while input 113 of MOS device 103 and input 128 of MOS device 123 remain low, pre-charge node 121 will not discharge into node 141 and node 142 because any stray capacitances associated with those nodes have been pre-charged. However, the requirement that inputs 112, 113, 127, and 128 be allowed to assume their logic levels at any time during the evaluate phase, can cause the solution embodied in dynamic logic circuit 200 to be ineffective in eliminating noise in the operation of dynamic logic circuit 200.
If, during the evaluate phase, the low to high transition of input 112 of MOS device 102 and input 127 of MOS device 122 are sufficiently delayed relative to the beginning of the evaluate phase, then a false switching of the output of logic circuit 200 may still occur. In this circumstance, leakage can drain the pre-charge from node 141 and node 142 before the low to high transition of input 112 and input 127. Then, the pre-charge on node 121 will still be required to charge any stray capacitances of node 141 and 142, and the charge sharing that gave rise to the noise in the operation of dynamic logic circuit 100 of FIG. 1 will reappear. Consequently, dynamic logic circuit 200 is also susceptible to charge sharing noise. Therefore, there remains a need in the art for dynamic logic circuitry which eliminates charge sharing noise.